The fine delay adjust is implemented in an analog block, which uses a programmable current and a selectable number of capacitors, to create a voltage ramp. When integrated by the capacitor(s), the current will create a voltage which increases linearly with time (a voltage ramp). The higher the current, the faster the voltage will increase. The more capacitors selected, the slower the voltage will increase. By selecting an appropriate current value, and number of capacitors, a ramp with a desired voltage-vs-time ramp is created. This sets the full-scale delay time.
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No. The phase offset, or coarse delay, adjustment on the AD951x is a function built into the divider for each output. Depending upon the selected divide ratio, there are from 2 to 32 edges of the incoming clock which can be chosen as the trigger edge for the output. This allows for setting a phase offset, or time delay, between outputs. This feature is entirely contained within the divider block itself. These dividers are designed so that this feature does not affect the jitter of the output. The jitter performance of the output will be the same regardless of the phase offset (coarse delay) selected.
Yes. It is very possible to turn off unused sections of the AD951x chips. There is a high degree of configuration which allows unused inputs, outputs, and the PLL to be powered off when not needed or not used. The programming register table shows the bits which control these power downs.
Have you thought about using the edge selection (coarse phase adjust)? This feature will allow you to specify which rising edge on the reference clock generates the rising edge in your output. The resolution of this adjustment feature is the system clock period, which can be sufficient for many applications. This feature is available on all channels. Use of the edge select has no impact on the jitter of the output channel.
When the phase noise values for your VCO/VCXO are known, use ADIsimCLK to simulate the jitter performance of the ADI clock distribution IC using that component. For VCO/VCXO parts which are not yet included in the ADIsimCLK library, the phase noise can be manually entered in the appropriate spot in the program's user interface, and the simulations continued. The effect of various amounts of VCO/VCXO phase noise can easily be seen and appreciated in the results given by ADIsimCLK. This will help you to determine a suitable candidate for your VCO/VCXO.
Yes. Most RF mixers do not convey amplitude information from the LO, just the phase and frequency. In this sense, the output of the clock drivers makes a great programmable LO source, up to their maximum frequency capability. 2ff7e9595c